HxS Release 1.0.12
31.08.2023 Denis Vasilík
We are excited to unveil HxS 1.0.12. It is now available for download. Discover a range of exciting new features such as AXI4-Lite support and improvements for IP-XACT.
- AXI4-Lite
- IP-XACT VHDL Wrapper
- Bus Reset Objects
- SPI Controller Example
- Eclipse Plugin and VS Code Extension
AXI4-Lite
After months of development and verification we added our
third bus interface AXI4-Lite. Setting the BusType
property of an interface
to BusType.AXI4Lite
is enough to create an AXI4-Lite register interface.
interface MyInterface
{
BusType = BusType.AXI4Lite;
}
An AXI4-Lite HxS example can be found at the playground.
IP-XACT VHDL Wrapper
We always strive to reduce complexity and to keep tedious work
away from developers. Therefore, we introduced the vhdl.ipxact.wrapper
annotation. It instructs the VHDL generater to create a VHDL
entity without any records for use by IP-XACT. The annotation
is part of an interface
object and can be used as
follows.
@Generator('vhdl.ipxact.wrapper', 'true')
interface MyInterface { }
Bus Reset Objects
We added the following bus reset objects to the HxS Base Library:
- BusReset.None - Bit field is not affected by bus reset
- BusReset.Sync - Bit field is affected by synchronous bus reset
- BusReset.Async - Bit field is affected by asynchronous bus reset
data MyData
{
Width = 4;
Resets = [
BusReset.None,
MySoftReset0,
MySoftReset1
];
}
The dictionary syntax can be used as well. It enhances the readability if multiple resets are defined. Here is an example:
data MyData
{
Width = 4;
Resets = {
0xU : BusReset.None,
0x5 : MySoftReset0,
0xF : MySoftReset1
};
}
Further information about the reset behaviour can be found in the documentation of the data and enum objects.
SPI Controller Example
In addition to the smaller examples at the playground, we continuously add practical examples to our the publicly available repository at GitHub. This time we added a SPI controller example, which shows advanced features of HxS.
Eclipse Plugin and VS Code Extension
We update the HxS Eclipse plugin and VS Code extension with each release. Both IDE integrations are available at the download section.
HxS Release 1.0.11
30.06.2023 Denis Vasilík
Great news! HxS 1.0.11 is now available for download. Discover a range of exciting new features and improvements.
- Added IP-XACT Extension
- Added Annotation for Identifier Customization
- Added a Playground
- Added Example Projects on GitHub
- Fixed Synchronous Registers with Asynchronous Properties
Added IP-XACT Extension
In order to improve our efforts for making HxS even more useful we added the IP-XACT extension. It can be used as follows:
~$ hxsc -o src-gen ipxact src/MyInterface.hxs
The IP-XACT extension supports the standards spirit._1685_2009
,
and accellera._1685_2014
. By default, the extension generates
IP-XACT files compliant to the accellera._1685_2014
standard.
It can be changed using an annotation for the interface
.
@Generator('ipxact.standard', 'spirit._1685_2009')
interface MyInterface { }
We are eager to improve the IP-XACT extension with each future release, so if you have any ideas how we might improve let us know.
Added Annotation for Identifier Customization
The VHDL, Python and C generators support the
{vhdl, python, c}.naming.scope
annotation to
influence the creation of identifers. By default, generators
create identifiers that are unique and short in length.
Depending on the use case, it might be necessary to customize
the creation of identifers. The annotation can be used as follows:
@Generator('vhdl.naming.scope', 'interface')
interface MyInterface
{
Blocks = [MyBlock];
}
block MyBlock
{
Registers = [MyRegister];
}
register MyRegister
{
Bits = [MyData];
}
data MyData
{
Width = 8;
}
The example above will create the following identifiers for the VHDL package. The parts that are bold are influenced by the annotation.
constant MYINTERFACE_MYBLOCK_BASE_ADDRESS : std_logic_vector(31 downto 0) := x"00000000";
constant MYINTERFACE_MYBLOCK_SIZE : std_logic_vector(31 downto 0) := x"00000001";
constant MYINTERFACE_MYBLOCK_MYREGISTER_WIDTH : integer := 8;
constant MYINTERFACE_MYBLOCK_MYREGISTER_ADDRESS : std_logic_vector(31 downto 0) := std_logic_vector(x"00000000" + unsigned(MYINTERFACE_MYBLOCK_BASE_ADDRESS));
constant MYINTERFACE_MYBLOCK_MYREGISTER_MYDATA_MASK : std_logic_vector(7 downto 0) := x"FF";
Using the interface
scope will create the longest
identifers, but ensures uniqueness. Further details and examples
can be found in the
documentation.
Added a Playground
In order to get to know HxS and its capabilities, we have created a playground that shows small examples of register interfaces and their corresponding HxS compiler output. The playground can be found here.
Example Projects on GitHub
In addition to our playground that provides small examples for learning purposes, we continuously work on repositories on GitHub offering practical examples.
Fixed Synchronous Registers with Asynchronous Properties
If a register
has been defined as synchronous, but
has asynchronous properties like AsyncClk
, AsyncRst
,
ReadAckDelay
or WriteAckDelay
,
the generator has not ignored them. This lead to invalid VHDL
code and has been fixed in this release. In addition, a warning
is shown in case a register mixes synchronous and asynchronous
properties.
register MyRegister
{
Async = false; // Default value
AsyncClk = "MyAsyncClkSignalName"; // Is ignored, because Async = false
AsyncRst = "MyAsyncRstSignalName"; // Is ignored, because Async = false
ReadAckDelay = 3; // Is ignored, because Async = false
WriteAckDelay = 3; // Is ignored, because Async = false
}
HxS Release 1.0.10
24.05.2023 Denis Vasilík
We are happy to release HxS 1.0.10. It comes with a bunch of new features and is available at our download section.
- Added annotations for VHDL comments
- Added HxS release version to CLI
- Added VS Code content assist and documentation
Added annotations for VHDL comments
We added annotations to activate Doxygen comments for the VHDL
code generation. There are three possible options;
none
, brief
and detailed
.
none
is the default option and disables the
generation of Doxygen comments. brief
adds a short
description and detailed
a detailed description
to the generated VHDL code. The following example shows how to
activate Doxygen comments for the VHDL generator:
@Generator('vhdl.comments.doxygen', 'detailed')
interface MyInterface
{
Name = 'MyInterface';
Description = 'My interface description.';
Blocks = [MyBlock];
}
It is important to note that comments are only provided for the generated VHDL package. For further information about annotations, please refer to the HxS Annotations documentation.
Added HxS release version to CLI
In order to improve the version management, we added the HxS
release version in addition to the HxS compiler version to
the command line interface. It can be accessed using the
--version
option.
HxS 1.0.10
HxS Compiler 1.0.16-502deb34
Copyright (C) 2023 Eccelerators GmbH
To list the versions of all installed HxS extensions, the
--extensions
option can be used.
Extensions Path: /home/developer/.hxs/extensions
Extensions:
C (c) 1.0.21-830987e7
Docs (docs) 1.0.15-803f34cc
Python (python) 1.0.4-f55ac08b
simstm (simstm) 1.0.9-e0eeca02
VHDL (vhdl) 1.0.18-dc735325
Added VS Code content assist and documentation
We continuously improve the usability of HxS. In this release, we focused on the VS Code extension. The extension is now able to provide content assist and documentation for HxS objects. The latest VS Code extension is available at the Visual Studio Marketplace .
HxS Release 1.0.9
28.04.2023 Denis Vasilík
We are happy to release HxS 1.0.9. It comes with a bunch of new features and is available at our download section.
- Added CLI Error Codes to HxS Compiler
- Changed Default Behaviour for Asynchronous Registers
- Added Snake Case Support to VHDL
- Highlight Bus Reset in Eclipse
Added CLI Error Codes to HxS Compiler
In order to check error conditions of the HxS compiler, we added error codes to the CLI application. The following error codes are available:
- 0 - No error
- 1 - Unknown error
- 2 - Input file or path not found
- 3 - Invalid license file
- 4 - Unknown extension error
- 5 - Input file validation error
It is important to note that the HxS compiler always exits gracefully logging detailled error information to the log file.
Changed Default Behaviour for Asynchronous Registers
In order to simplify the usage of asynchronous registers, the
default behaviour has been changed. From now on, the
asynchronous feedback acknowledge is used as default for both
read and write acknowledge signals. This behaviour is
overriden by an external acknowledge or delay. In order to use
another acknowledge signal, the ReadExternalAck
or WriteExternalAck
property has to be used. The
following example shows how to use an external acknowledge
signal and acknowledge delay instead of an asynchronous feedback:
register MyRegister
{
Async = true;
ReadExternalAck = true;
WriteAckDelay = 3;
Bits = [MyData];
}
Added Snake Case Support to VHDL
In order to support different naming conventions, the VHDL generator now supports snake case. The following example shows how to use snake case for the VHDL generator:
@Generator('vhdl.letter_case', 'snake_case')
interface MyInterface
{
DataBusWidth = 32;
AddressBusWidth = 32;
Blocks = [MyBlock];
BusType = BusType.Avalon;
}
Highlight Bus Reset in Eclipse
The first reset in a data or enum object's Resets
list determines the bus reset. In order to emphasize the special
meaning, we now highlight the bus reset in Eclipse and provide
additional information. The following examples shows a data
object with bus reset and additional reset signal:
data MyData
{
Resets = [
MyBusReset,
MyAdditionalReset
];
}
Further information about the reset behaviour can be found in the
documentation of the data
and enum objects.
The latest Eclipse plugin is available at our download section.
HxS Release 1.0.8
31.03.2023 Denis Vasilík
We are happy to release HxS 1.0.8. It comes with a bunch of new features and is available at our download section.
Added Avalon Bus Interface
It is now possible to switch between Wishbone and Avalon bus
interfaces. Therefore, we added a new property named BusType
to the interface
object. Setting BusType.Avalon
will create a bus interface for Avalon as can be seen below.
namespace MyNamespace
{
interface MyInterface
{
BusType = BusType.Avalon;
}
}
The following entity will be created providing AvalonDown
and AvalonUp
records for the bus connection.
entity MyInterfaceAvalon is
port (
Clk : in std_logic;
Rst : in std_logic;
AvalonDown : in T_MyInterfaceAvalonDown;
AvalonUp : out T_MyInterfaceAvalonUp;
Trace : out T_MyInterfaceTrace; -- optional
Selects : in T_MyInterfaceSelects; -- optional
MyInterfaceBlockDown : out T_MyInterfaceBlockDown; -- optional
MyInterfaceBlockUp : out T_MyInterfaceBlockUp -- optional
);
end;
Have a look at the Interface section of our documentation for further information.
Added Python Extension
In addition to the C extension we added a Python extension that generates variables for addresses, offsets, sizes and masks making the code more readable and enhancing the productivity of Python users.
~$ hxsc -o src-gen-python python src/MyInterface.hxs
Added --format / -f
option to HxS Compiler CLI
In addition to use the auto-formatter of our IDE plugins it
is now possible to use the hxsc
CLI tool to format
HxS files. This is especially useful for CI / CD pipelines
or pre-commit hooks in order to enforce auto-formatting of
HxS files.
~$ hxsc --format src/MyInterface.hxs
HxS Release 1.0.7
03.03.2023 Denis Vasilík
We are happy to release HxS 1.0.7. It comes with a bunch of new features and is available at our download section.
- Added external Acknowledge Signals
- Added Feedback for Asynchronous Acknowledge
- Added Content Assist to HxS Extension for VS Code
- Fixed Multi-File References of HxS Plugin for Eclipse
Added external Acknowledge Signals
Registers can now have external acknowledge signals for read or write accesses. They are enabled using the ReadExternalAck or WriteExternalAck properties. Further information is available in our documentation of Registers.
namespace MyNamespace
{
register MyRegister
{
ReadExternalAck = true;
WriteExternalAck = true;
}
}
Added Feedback for Asynchronous Acknowledge
It is now possible to specify whether to feedback the acknowledge signal for asynchronous read or write accesses.
namespace MyNamespace
{
@Generator('vhdl.use_async_read_ack_feedback', 'true')
@Generator('vhdl.use_async_write_ack_feedback', 'true')
register MyRegister
{
ReadExternalAck = true;
WriteExternalAck = true;
}
}
Added Content Assist to HxS Extension for VS Code
We continuously improve the HxS extension for VS Code. This time we implemented the content assist feature, so that properties of HxS objects are shown in the editor.
Fixed Multi-File References of HxS Plugin for Eclipse
We fixed a bug were the HxS plugin for Eclipse was unable to resolve references to HxS objects located in different files.
HxS Release 1.0.6
24.02.2023 Denis Vasilík
We are proud to release HxS 1.0.6. It comes with a bunch of new features and is available at our download section.
- Changed Wishbone bus interface signal and type names
- Added support for Block, Register and Delegate selects
- Added a bus monitor for VHDL bus interfaces
- Added a configuration file for the HxS compiler
- Improved error handling of the HxS compiler
Bus Interface Signal and Type Names
We strive at continuous improvement and therefore we updated the signal and type names of the Wishbone bus interface. It is now concise, easily readable and consists of exactly the information needed. Please note that this is a breaking change and existing consumers of the Wishbone bus interface must be updated.
entity ExampleWishbone is
port (
Clk : in std_logic;
Rst : in std_logic;
WishboneDown : in T_ExampleWishboneDown;
WishboneUp : out T_ExampleWishboneUp;
Trace : out T_ExampleTrace; -- optional
Selects : in T_ExampleSelects; -- optional
ExampleBlockDown : out T_ExampleBlockDown; -- optional
ExampleBlockUp : out T_ExampleBlockUp -- optional
);
end;
Block, Register and Delegate Selects
Block, register and delegate selects have been added to provide additional signals for bus access multiplexing. Detailed information is available in our documentation of Blocks, Registers and Delegates.
block MyBlock
{
Selects = [MySelect];
}
register MyRegister
{
Selects = [MySelect];
}
delegate MyDelegate
{
Selects = [MySelect];
}
select MySelect
{
Behaviour = SelectBehaviour.ReadWrite;
}
Bus Monitor
The task of the bus monitor is to prevent any blocking of the bus. In addition, it provides diagnostics about bus usage behaviour such as illegal addresses or access timeouts. Diagnostic information can be accessed using the Trace record provided by the bus interface.
entity ExampleWishbone is
port (
Clk : in std_logic;
Rst : in std_logic;
WishboneDown : in T_ExampleWishboneDown;
WishboneUp : out T_ExampleWishboneUp;
Trace : out T_ExampleTrace;
Selects : in T_ExampleSelects;
ExampleBlockDown : out T_ExampleBlockDown;
ExampleBlockUp : out T_ExampleBlockUp
);
end;
Configuration File
The HxS compiler uses now a configuration file in order to specify settings of HxS generators. The file is named hxsc.properties and is located in the HxS installation directory. The --config compiler argument shows a list of available configuration settings. It is notable that the list of configurations depend on HxS compiler extensions installed.
~$ hxsc --config
# Configuration path: /home/eccelerators/.hxs/hxsc.properties
c.api.url=https://api.eccelerators.com
docs.api.url=https://api.eccelerators.com
simstm.api.url=https://api.eccelerators.com
vhdl.api.url=https://api.eccelerators.com
Improved Error Handling
The HxS compiler now handles internal errors more gracefully without dumping stack traces to the console. Detailed error information is written into a log file that is located in the installation directory at logs/hxsc.log.