Livt packages

Eccelerators.Matrix

Version 1.0.1

Reusable RGB matrix drawing, color conversion, animation pacing, and HUB75 display components for Livt.

Published files (48)

tests/Hub75Color6Test.lvt

namespace Eccelerators.Matrix.Tests

using Eccelerators.Matrix
using Eccelerators.Matrix.Hub75

/**
 * Verify six RGB666 planes in the inherited 50 MHz context.
 * Observe two complete frames and independently check binary dwell weighting.
 */
@Test
@Context(ClockFrequency = 50MHz)
component Hub75Color6Test
{
	// Independent expected lane bits and dwell clocks, least-significant plane first.
	const UPPER: byte[6] = [3, 5, 2, 4, 3, 5,]
	const DWELL: int[6] = [119, 238, 476, 952, 1904, 3808,]

	// Owned scanner under test.
	core: Hub75Controller<8, 1, 100ns, 1us, 1us, 6, 150us>

	// Edge timestamps and previous signal levels for timing measurements.
	cycles: int
	rise: int
	enabled: int
	oldClock: logic
	oldEnable: logic = 0b1
	pulses: int
	rows: int

	/**
	 * Own the scanner with physical durations and inherit this test clock.
	 */
	new()
	{
		this.core = new Hub75Controller<8, 1, 100ns, 1us, 1us, 6, 150us>()
	}

	/**
	 * Supply distinct channel bits to exercise all six PWM planes.
	 */
	process Connect[]()
	{
		this.core.pixelUpper = 0x2A573 as logic[18]
		this.core.pixelLower = 0x15A8C as logic[18]
	}

	/**
	 * Measure clock-high, shift-period and enabled-dwell lengths in context edges.
	 */
	process Monitor()
	{
		state {
			this.cycles++

			if (this.core.frameBoundary == 0b1) {
				assert this.rows % 12 == 0
			}

			if (this.core.panelClock == 0b1 && this.oldClock == 0b0) {
				if (this.pulses % 8 != 0) {
					assert this.cycles - this.rise == 15
				}

				assert this.core.row == (((this.rows / 6) % 2) as logic[1])
				assert this.core.rgbUpper == (UPPER[this.rows % 6] as logic[3])
				assert this.core.rgbLower == (((this.core.rgbUpper as uint) ^ 7) as logic[3])
				this.rise = this.cycles
				this.pulses++
			}

			if (this.core.panelClock == 0b0 && this.oldClock == 0b1) {
				assert this.cycles - this.rise == 5
			}

			if (this.core.outputEnableN == 0b0 && this.oldEnable == 0b1) {
				this.enabled = this.cycles
			}

			if (this.core.outputEnableN == 0b1 && this.oldEnable == 0b0) {
				assert this.cycles - this.enabled == DWELL[this.rows % 6]
				this.rows++
			}

			this.oldClock = this.core.panelClock
			this.oldEnable = this.core.outputEnableN
		}
	}

	/**
	 * Wait for twenty-four plane dwells while checking channel bits, row order and timing.
	 */
	@Test
	fn PreservesPhaseAndDwellTiming()
	{
		while (this.rows < 24) {
		}
	}
}