Livt packages

Eccelerators.RiscV

Version 0.3.0

Composable RV32I and Zmmul processors, machine-mode support, and reusable FPGA system components written in Livt.

Published files (120)

src/Machine/IRv32MachineControlPort.lvt

namespace Eccelerators.RiscV.Machine

using Eccelerators.RiscV.Sequential

/**
 * Execution control plus synchronous persistent machine interrupt levels.
 * The platform owns source acknowledgement; core restart does not clear sources.
 */
interface IRv32MachineControlPort : IRv32ControlPort
{
	// Already synchronized pending levels, held until the source is serviced.
	timerPending: in logic
	externalPending: in logic
}