Eccelerators.RiscV

src/Presets/Rv32iPipelineCore.lvt

namespace Eccelerators.RiscV.Presets

using Eccelerators.RiscV.Sequential
using Eccelerators.RiscV.Machine
using Eccelerators.RiscV.Pipeline
using Eccelerators.RiscV.Storage
using Eccelerators.RiscV.Contracts
using Livt.IO

/**
 * Named RV32I pipelined composition: combinational decoder/integer unit and a
 * dual-read register bank (BRAM by default). Borrows instruction/data providers exclusively
 * in the same clock/reset domain. Qualification applies to the documented memory
 * providers and target, not to arbitrary buses supplied through these interfaces.
 */
component Rv32iPipelineCore<RESET_PC: uint = 0, REGISTER_FILE_STYLE: MemoryStyle = MemoryStyle.Block> : IRv32ControlPort
{
	// Owned execution components and elaboration-only compatibility checks.
	registers: Rv32DualReadRegisterBank<REGISTER_FILE_STYLE>
	decoder: Rv32iDecoder
	integer: Rv32iIntegerUnit
	noMultiplier: Rv32NoMultiplier
	noCsrs: Rv32NoCsrs
	engine: Rv32PipelineEngine<RESET_PC>

	// Elaboration-only checks for operation coverage and provider timing.
	coverage: RvOperationCoverage<Rv32iDecode.CAPABILITIES, Rv32iDecoder.CAPABILITIES,
		Rv32iIntegerUnit.CAPABILITIES, Rv32PipelineEngine.CAPABILITIES,
		Rv32iOperations.INTEGER_CAPABILITY, Rv32PipelineEngine.CAPABILITIES>
	timing: RvPipelineContract<Rv32DualReadRegisterBank.READ_PORTS,
		Rv32DualReadRegisterBank.READ_LATENCY, Rv32DualReadRegisterBank.INDEPENDENT_WRITE,
		Rv32DualReadRegisterBank.WRITE_FORWARDING>

	/**
	 * Owns the CPU internals; the caller owns both bus providers.
	 */
	new(fetch: flip IRv32FetchPort, loadStore: flip IRv32LoadStorePort)
	{
		registers = new Rv32DualReadRegisterBank<REGISTER_FILE_STYLE>()
		decoder = new Rv32iDecoder()
		integer = new Rv32iIntegerUnit()
		noMultiplier = new Rv32NoMultiplier()
		noCsrs = new Rv32NoCsrs()
		engine = new Rv32PipelineEngine<RESET_PC>(registers, fetch, loadStore, decoder, integer, noMultiplier, noCsrs)
		coverage = new RvOperationCoverage<Rv32iDecode.CAPABILITIES, Rv32iDecoder.CAPABILITIES,
			Rv32iIntegerUnit.CAPABILITIES, Rv32PipelineEngine.CAPABILITIES,
			Rv32iOperations.INTEGER_CAPABILITY, Rv32PipelineEngine.CAPABILITIES>()
		timing = new RvPipelineContract<Rv32DualReadRegisterBank.READ_PORTS,
			Rv32DualReadRegisterBank.READ_LATENCY, Rv32DualReadRegisterBank.INDEPENDENT_WRITE,
			Rv32DualReadRegisterBank.WRITE_FORWARDING>()
	}

	/**
	 * Pure wiring preserves the engine's edge-level control and retirement contract.
	 */
	process Connect[]()
	{
		engine.run = run
		engine.stepRequest = stepRequest
		engine.restartRequest = restartRequest
		stepAck = engine.stepAck
		restartAck = engine.restartAck
		idle = engine.idle
		halted = engine.halted
		pc = engine.pc
		faultCause = engine.faultCause
		faultValue = engine.faultValue
		trapped = engine.trapped
		trapPc = engine.trapPc
		trapCause = engine.trapCause
		trapValue = engine.trapValue
		retired = engine.retired
		retiredPc = engine.retiredPc
		retiredInstruction = engine.retiredInstruction
		retiredRd = engine.retiredRd
		retiredValue = engine.retiredValue
	}
}