Livt packages

Eccelerators.RiscV

Version 0.3.0

Composable RV32I and Zmmul processors, machine-mode support, and reusable FPGA system components written in Livt.

Published files (120)

src/Sequential/IRv32LoadStorePort.lvt

namespace Eccelerators.RiscV.Sequential

/**
 * One-clock-domain, one-outstanding aligned word load/store transaction, consumer to provider.
 * Hold request/address/write/mask/data stable until an edge with ready=1. That edge
 * completes exactly once; sample readData/error there, then deassert request for at
 * least one edge. Provider must reject errors before effects and not accept again
 * until request falls. No cancellation; software restart drains outstanding work.
 * Byte lane zero is bits 7..0. A read ignores mask; write mask zero has no effect.
 */
interface IRv32LoadStorePort
{
	// Consumer-owned request, stable throughout the transaction.
	request: in logic
	address: in logic[32]
	write: in logic
	byteEnable: in logic[4]
	writeData: in logic[32]

	// Provider-owned completion, held until request deasserts.
	ready: out logic
	error: out logic
	readData: out logic[32]
}