Livt packages

Eccelerators.RiscV

Version 0.3.0

Composable RV32I and Zmmul processors, machine-mode support, and reusable FPGA system components written in Livt.

Published files (120)

src/Sequential/IRv32MultiplyPort.lvt

namespace Eccelerators.RiscV.Sequential

/**
 * One outstanding multiplication, exclusively borrowed in one clock/reset domain.
 * A high request accepts stable operation/operands on an idle edge. Keep request
 * high through completion; ready/result then remain stable until a low-request
 * edge releases the transaction. No reacceptance while request remains high.
 * Operation is the Zmmul funct3 (0..3). The caller must not issue other values.
 * Hardware reset cancels work and clears ready; caller also resets/deasserts its
 * request. No software cancellation. Only the engine commits architectural state.
 */
interface IRv32MultiplyPort
{
	// Stable command through the completion sampling edge.
	request: in logic
	operation: in logic[2]
	left: in logic[32]
	right: in logic[32]

	// Completion remains asserted until a low-request edge.
	ready: out logic
	result: out logic[32]
}