Livt packages

Eccelerators.RiscV

Version 0.3.0

Composable RV32I and Zmmul processors, machine-mode support, and reusable FPGA system components written in Livt.

Published files (120)

src/Sequential/Rv32iDecoder.lvt

namespace Eccelerators.RiscV.Sequential

/**
 * Combinational decoder component, sharing pure semantics with other engines/tests.
 * Outputs continuously reflect instruction; the owner controls sampling boundaries.
 */
component Rv32iDecoder : IRv32DecodePort
{
	// Concrete implementation capabilities used by the composition contract.
	public const CAPABILITIES: uint = Rv32iDecode.CAPABILITIES

	/**
	 * Continuously computes decoded control and immediate without state.
	 */
	process Decode[]()
	{
		control = Rv32iDecode.Control(instruction as uint) as logic[32]
		immediate = Rv32iDecode.Immediate(instruction as uint) as logic[32]
	}
}