Eccelerators.RiscV

src/Sequential/Rv32iOperations.lvt

namespace Eccelerators.RiscV.Sequential

/**
 * Shared RV32I semantic identifiers. Decode operation byte packs kind in its high
 * nibble and integer operation in its low nibble; capability bits denote families.
 */
public class Rv32iOperations
{
	// Execution families for construction checks.
	public const INTEGER_CAPABILITY: uint = 1
	public const MEMORY_CAPABILITY: uint = 2
	public const CONTROL_CAPABILITY: uint = 4
	public const RV32I_CAPABILITIES: uint = 7

	// Packing and unsupported-operation sentinel for the decoded operation byte.
	public const KIND_SHIFT: int = 4
	public const ALU_MASK: uint = 15
	public const INVALID_ALU: uint = 255

	// Branch funct3 encodings used by the base integer ISA.
	public const BEQ: uint = 0
	public const BNE: uint = 1
	public const BLT: uint = 4
	public const BGE: uint = 5
	public const BLTU: uint = 6
	public const BGEU: uint = 7

	// Memory funct3 encodings; stores use the same low width bits as signed loads.
	public const BYTE: uint = 0
	public const HALF: uint = 1
	public const WORD: uint = 2
	public const BYTE_UNSIGNED: uint = 4
	public const HALF_UNSIGNED: uint = 5
	public const WIDTH_MASK: uint = 3

	// Exact base system encodings, separate from future CSR/privileged extensions.
	public const ECALL_ENCODING: uint = 0x00000073
	public const EBREAK_ENCODING: uint = 0x00100073

	// Operation categories, packed in the high nibble.
	public const ILLEGAL: uint = 0
	public const REGISTER: uint = 1
	public const IMMEDIATE: uint = 2
	public const LUI: uint = 3
	public const AUIPC: uint = 4
	public const JAL: uint = 5
	public const JALR: uint = 6
	public const BRANCH: uint = 7
	public const LOAD: uint = 8
	public const STORE: uint = 9
	public const FENCE: uint = 10
	public const ECALL: uint = 11
	public const EBREAK: uint = 12

	// Integer datapath operations, packed in the low nibble.
	public const ADD: uint = 0
	public const SUB: uint = 1
	public const SLL: uint = 2
	public const SLT: uint = 3
	public const SLTU: uint = 4
	public const XOR: uint = 5
	public const SRL: uint = 6
	public const SRA: uint = 7
	public const OR: uint = 8
	public const AND: uint = 9

	// Fault-stop causes follow architectural cause numbers; machine trap entry is absent.
	public const INSTRUCTION_MISALIGNED: uint = 0
	public const INSTRUCTION_ACCESS: uint = 1
	public const ILLEGAL_INSTRUCTION: uint = 2
	public const BREAKPOINT: uint = 3
	public const LOAD_MISALIGNED: uint = 4
	public const LOAD_ACCESS: uint = 5
	public const STORE_MISALIGNED: uint = 6
	public const STORE_ACCESS: uint = 7
	public const ENVIRONMENT_CALL: uint = 11
}