Livt.Bus

src/IMemoryMappedBus32.lvt

namespace Livt.Bus

/**
 * Transaction-level access to a 32-bit, byte-addressed memory-mapped bus.
 */
interface IMemoryMappedBus32 : IMemoryMappedMaster32
{
	/**
	 * Writes one byte to the selected byte address and asserts successful completion.
	 */
	fn Write8(address: uint, value: byte)

	/**
	 * Writes one aligned halfword and asserts successful completion.
	 */
	fn Write16(address: uint, value: Logic[16])

	/**
	 * Writes one aligned 32-bit word and asserts successful completion.
	 */
	fn Write32(address: uint, value: uint)

	/**
	 * Writes selected byte lanes of an aligned word and asserts successful completion.
	 */
	fn WriteMasked32(address: uint, value: uint, byteEnable: Logic[4])

	/**
	 * Reads and returns the byte at the selected byte address.
	 */
	fn Read8(address: uint) byte

	/**
	 * Reads and returns the aligned halfword at the selected byte address.
	 */
	fn Read16(address: uint) Logic[16]

	/**
	 * Reads and returns one aligned 32-bit word.
	 */
	fn Read32(address: uint) uint

	/**
	 * Reads one byte and asserts that it equals the expected value.
	 */
	fn Verify8(address: uint, expected: byte)

	/**
	 * Reads one halfword and asserts that it equals the expected value.
	 */
	fn Verify16(address: uint, expected: Logic[16])

	/**
	 * Reads one aligned word and asserts that it equals the expected value.
	 */
	fn Verify32(address: uint, expected: uint)

	/**
	 * Reads one aligned word and compares only the bits selected by the mask.
	 */
	fn VerifyMasked32(address: uint, expected: uint, mask: uint)
}