Livt packages

Livt.Bus

Version 2.0.1

Configurable Avalon, AXI4-Lite, and Wishbone memory-mapped masters, interfaces, bridges, and test components.

Published files (67)

src/IMemoryMappedMaster.lvt

namespace Livt.Bus

/**
 * Full-width byte-addressed transactions. Data and addresses never pass through uint.
 */
interface IMemoryMappedMaster<Address, Data, ByteEnable>
{
	fn SetTimeoutTicks(timeoutTicks: uint)

	fn GetTimeoutTicks() uint

	fn TryWrite(address: Address, value: Data, byteEnable: ByteEnable) bool

	fn TryRead(address: Address) bool

	fn TryReadMasked(address: Address, byteEnable: ByteEnable) bool

	fn LastReadValue() Data

	fn LastResponse() Logic[2]

	fn LastTimedOut() bool
}