Livt packages

Livt.Bus

Version 2.0.1

Configurable Avalon, AXI4-Lite, and Wishbone memory-mapped masters, interfaces, bridges, and test components.

Published files (67)

tests/avalon/AvalonTestMasterTest.lvt

namespace Livt.Bus.Tests.Avalon

using Livt.Bus.Avalon.Testing

@Test
component AvalonTestMasterTest
{
	master: AvalonTestMaster32
	slave: AvalonTestSlave32

	new()
	{
		this.master = new AvalonTestMaster32()
		this.slave = new AvalonTestSlave32(this.master)
	}

	@Test
	fn ExercisesVerificationApi()
	{
		slave.Clear()
		var timeoutTicks = this.context.TicksFor(2us)
		master.SetTimeoutTicks(timeoutTicks)
		assert master.GetTimeoutTicks() == timeoutTicks
		slave.Configure(2 as uint, 0b00)

		master.Write32(0x04 as uint, 0x11223344 as uint)
		master.Verify32(0x04 as uint, 0x11223344 as uint)
		master.WriteMasked32(0x04 as uint, 0xAA00CC00 as uint, 0b1010)
		master.VerifyMasked32(0x04 as uint, 0xAA22CC44 as uint, 0xFFFFFFFF as uint)

		master.Write8(0x05 as uint, 0x5A as byte)
		master.Verify8(0x05 as uint, 0x5A as byte)
		assert master.Read8(0x05 as uint) == (0x5A as byte)

		master.Write16(0x06 as uint, 0xCAFE as Logic[16])
		master.Verify16(0x06 as uint, 0xCAFE as Logic[16])
		assert master.Read16(0x06 as uint) == (0xCAFE as Logic[16])
		assert master.Read32(0x04 as uint) == (0xCAFE5A44 as uint)
	}

	@Test
	fn ExposesNonAssertingResponseApi()
	{
		slave.Configure(0 as uint, 0b10)
		assert master.TryRead32(0x04 as uint) == true
		assert master.LastResponse() == 0b10
		assert master.LastTimedOut() == false

		master.SetTimeoutTicks(2 as uint)
		slave.Configure(20 as uint, 0b00)
		assert master.TryWrite32(0x08 as uint, 0x12345678 as uint, 0b1111) == false
		assert master.LastTimedOut() == true
		slave.Configure(0 as uint, 0b00)
		master.SetTimeoutTicks(10 as uint)
		assert master.TryRead32(0x08 as uint) == true
		assert master.LastReadValue() == (0x12345678 as uint)
	}
}