Livt.Bus

tests/axi4lite/Axi4LiteMasterTest.lvt

namespace Livt.Bus.Tests.Axi4Lite

using Livt.Bus.Axi4Lite
using Livt.Bus.Axi4Lite.Testing

@Test
component Axi4LiteMasterTest
{
	master: Axi4LiteMaster32
	slave: Axi4LiteTestSlave32

	new()
	{
		this.master = new Axi4LiteMaster32()
		this.slave = new Axi4LiteTestSlave32(this.master)
	}

	@Test
	fn RunsReusableTransactions()
	{
		slave.Clear()
		var timeoutTicks = this.context.TicksFor(2us)
		master.SetTimeoutTicks(timeoutTicks)
		slave.ConfigureDelays(2, 0, 2, 1, 2)

		assert master.TryWrite32(0x04 as uint, 0x12345678 as uint, 0b1111) == true
		assert master.LastResponse() == Axi4LiteMaster32.RESPONSE_OKAY
		assert master.TryRead32(0x04 as uint) == true
		assert master.LastReadValue() == (0x12345678 as uint)

		assert master.TryWrite32(0x04 as uint, 0x00AA00CC as uint, 0b0101) == true
		assert master.TryRead32(0x04 as uint) == true
		assert master.LastReadValue() == (0x12AA56CC as uint)
		assert master.LastTimedOut() == false

		slave.ConfigureResponses(0b10, 0b11)
		assert master.TryWrite32(0x08 as uint, 0xA5A55A5A as uint, 0b1111) == true
		assert master.LastResponse() == 0b10
		assert master.TryRead32(0x08 as uint) == true
		assert master.LastResponse() == 0b11

		assert master.awvalid == 0b0
		assert master.wvalid == 0b0
		assert master.bready == 0b0
		assert master.arvalid == 0b0
		assert master.rready == 0b0
	}

	@Test
	fn ReportsTimeout()
	{
		master.SetTimeoutTicks(2 as uint)
		slave.ConfigureResponses(0b00, 0b00)
		slave.ConfigureDelays(20, 20, 0, 0, 0)
		assert master.TryWrite32(0x00 as uint, 0x55AA55AA as uint, 0b1111) == false
		assert master.LastTimedOut() == true
		assert master.awvalid == 0b0
		assert master.wvalid == 0b0
		assert master.bready == 0b0

		// The timed-out write is drained without changing its payload.
		slave.ConfigureDelays(0, 0, 0, 0, 0)
		master.SetTimeoutTicks(10 as uint)
		assert master.TryRead32(0x00 as uint) == true
		assert master.LastReadValue() == (0x55AA55AA as uint)
		assert master.LastTimedOut() == false
	}
}