Livt packages

Livt.Usb

Version 0.0.5

USB 2.0 low/full-speed PHY, host transfers, device discovery, HID keyboard, and read-only mass storage for Livt.

Published files (57)

tests/RootPortTiming48Test.lvt

namespace Livt.Usb.Tests

using Livt.Usb
using Livt.Usb.Host

/**
 * Counts physical edges independently of the root port's duration calculations.
 * Expected counts are independent literal values for the 48 MHz test context.
 */
@Test
@Context(ClockFrequency = 48MHz)
component RootPortTiming48Test
{
	port: RootPort<10, 20, 30>
	resetTicks: uint
	frameTicks: uint
	frameSeen: bool
	frameError: bool

	/**
	 * Owns the root port under test in the inherited context.
	 */
	new()
	{
		port = new RootPort<10, 20, 30>()
	}

	/**
	 * Counts reset width and complete frame intervals without scheduled calls.
	 */
	process Measure()
	{
		state {
			if (port.busReset) { resetTicks++ }

			if (!port.connected) {
				frameTicks = 0
				frameSeen = false
			} elif (port.frameTick) {
				if (frameSeen && frameTicks != 47999) {
					frameError = true
				}

				frameSeen = true
				frameTicks = 0
			} else { frameTicks++ }
		}
	}

	/**
	 * Checks configured debounce/reset/recovery, frame spacing and SE0 disconnect.
	 */
	@Test
	fn PreservesDurations()
	{
		port.line = 2
		port.driving = false
		port.resetRequest = false
		Simulation.Wait(432)
		assert !port.busReset && !port.connected
		Simulation.Wait(96)
		assert port.busReset && port.speed == UsbSpeed.Full
		Simulation.Wait(960)
		assert !port.busReset && !port.connected
		assert resetTicks == 960
		Simulation.Wait(145488)
		assert port.connected
		assert frameSeen && !frameError
		port.line = 0
		Simulation.Wait(48)
		assert port.connected
		Simulation.Wait(144)
		assert !port.connected && port.speed == UsbSpeed.Unknown
	}
}